SNVSA37A October 2015 – May 2016 LM5175
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM5175 is a four-switch buck-boost controller. A quick-start tool on the LM5175 product webpage can be used to design a buck-boost converter using the LM5175. Alternatively, Webench®software can create a complete buck-boost design using the LM5175 and generate bill of materials, estimate efficiency, solution size, and cost of the complete solution. The following sections describe a detailed step-by-step design procedure for a typical application circuit.
A typical application example is a buck-boost converter operating from a wide input voltage range of 6 V to 36 V and providing a stable 12 V output voltage with current capability of 6 A.
For this design example, the following are used as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input Voltage Range | 6 V to 36 V |
Output | 12 V |
Load Current | 6 A |
Switching Frequency | 300 kHz |
Mode | CCM, Hiccup |
Click here to create a custom design using the LM5175 device with the WEBENCH® Power Designer.
The switching frequency of LM5175 is set by an R_{T} resistor connected from RT/SYNC pin to AGND. The R_{T} resistor required to set the desired frequency is calculated using Equation 5 or Figure 3 . A 1% standard resistor of 84.5 kΩ is selected for F_{sw} = 300 kHz.
The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally the bottom resistor in the resistor divider is selected to be in the 1 kΩ to 100 kΩ range. Select
The top resistor in the feedback resistor divider is selected using Equation 12:
The inductor selection is based on consideration of both buck and boost modes of operation. For the buck mode, inductor selection is based on limiting the peak to peak current ripple ΔI_{L} to ~40% of the maximum inductor current at the maximum input voltage. The target inductance for the buck mode is:
For the boost mode, the inductor selection is based on limiting the peak to peak current ripple ΔI_{L} to ~40% of the maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:
In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the converter by moving the right half plane zero to lower frequencies. Therefore a judicious compromise should be made based on the application requirements. For this design a 4.7-µH inductor is selected. With this inductor selection, the inductor current ripple is 5.7 A, 4.3 A, and 2.1 A, at V_{IN} of 36 V, 24 V, and 6 V respectively.
The maximum average inductor current occurs at the minimum input voltage and maximum load current:
where a 90% efficiency is assumed. The peak inductor current occurs at minimum input voltage and is given by:
To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in boost operation. To ensure that the inductor does not saturate in current limit, the peak saturation current of the inductor should be higher than the maximum current limit. Adjusting for a ±20% current limit threshold tolerance, the peak inductor current limit is:
Therefore, the inductor saturation current should be greater than 21.6 A. If hiccup mode protection is not enabled, the RMS current rating of the inductor should be sufficient to tolerate continuous operation in cycle-by-cycle current limiting.
In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is given by Equation 18 where the minimum V_{IN} corresponds to the maximum capacitor current.
In this example the maximum output ripple RMS current is I_{COUT(RMS)} = 6 A. A 5-mΩ output capacitor ESR causes an output ripple voltage of 60 mV as given by:
A 400 µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:
Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current capacity. The complete schematic in Figure 24 at the end of this section shows a good starting point for C_{OUT} for typical applications.
In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given by:
The maximum RMS current occurs at D = 0.5, which gives I_{CIN(RMS)} = I_{OUT}/2 = 3 A. A combination of ceramic and bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple. The complete schematic in Figure 24 is a good starting point for C_{IN} for typical applications.
The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is given by:
For the boost mode of operation, the current limit resistor is given by:
The closest standard value of R_{SENSE} = 8 mΩ is selected based on the boost mode operation.
The maximum power dissipation in R_{SENSE} happens at V_{IN(MIN)}:
Based on this, select the current sense resistor with power rating of 2 W or higher.
For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG sense lines. Please see Figure 24 for typical values. The filter resistance should not exceed 100 Ω.
For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected based on Equation 25:
This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated slope capacitor value in Equation 25). A smaller slope capacitor results in larger slope signal which is better for noise immunity in the transition region (V_{IN}~V_{OUT}). A larger slope signal, however, restricts the achievable input voltage range for a given output voltage, switching frequency, and inductor. For this design C_{SLOPE} = 100 pF is selected for better transition region behavior while still providing the required V_{IN} range. This selection of slope capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error Amplifier section.
The UVLO resistor divider must be designed for turn-on below 6V. Selecting a R_{UV2} = 249 kΩ gives a UVLO hysteresis of 0.8 V. The lower UVLO resistor is the selected using Equation 26:
A standard value of 59.0 kΩ is selected for R_{UV1}.
When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs with gate (Miller) plateau voltage lower than the minimum V_{IN}.
The soft-start time is programmed using the soft-start capacitor. The relationship between C_{SS} and the soft-start time is given by:
C_{SS} = 0.1 µF gives a soft-start time of 16 ms.
The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching frequency. A larger C_{DITH} results in lower modulation frequency. For proper operation the modulation frequency (F_{MOD}) must be much lower than the switching frequency. Use Equation 28 to select C_{DITH} for the target modulation frequency.
For the current design dithering is not being implemented. Therefore a 0 Ω resistor from the DITH pin to AGND disables this feature.
The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 36 V. In addition they must withstand the transient spikes at SW1 during switching. Therefore QH1 and QL1 should be rated for 60 V. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.
The power loss in QH1 in the boost mode of operation is approximated by:
The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss components given by Equation 30 and Equation 31 respectively:
The rise (t_{r}) and the fall (t_{f}) times are based on the MOSFET datasheet information or measured in the lab. Typically a MOSFET with smaller R_{DSON} (smaller conduction loss) will have longer rise and fall times (larger switching loss).
The power loss in QL1 in the buck mode of operation is given by the following equation:
The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2 during switching. Therefore QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.
The power loss in QH2 in the buck mode of operation is approximated by:
The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss components given by Equation 34 and Equation 35 respectively:
The rise (t_{r}) and the fall (t_{f}) times can be based on the MOSFET datasheet information or measured in the lab. Typically a MOSFET with smaller R_{DSON} (lower conduction loss) has longer rise and fall times (larger switching loss).
The power loss in QH2 in the boost mode of operation is given by the following equation:
This section presents the control loop compensation design procedure for the LM5175 buck-boost controller. The LM5175 operates mainly in buck or boost modes, separated by a transition region, and therefore the control loop design is done for both buck and boost operating modes. Then a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in the boost mode.
The boost power stage output pole location is given by:
where R_{OUT} = 2 Ω corresponds to the maximum load of 6 A.
The boost power stage ESR zero location is given by:
The boost power stage RHP zero location is given by:
where D_{MAX} is the maximum duty cycle at the minimum V_{IN}.
The buck power stage output pole location is given by:
The buck power stage ESR zero location is the same as the boost power stage ESR zero.
It is clear from Equation 39 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:
For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum duty cycle (D_{MAX}) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (f_{RHP}/3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.
The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:
If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the crossover, the compensation gain resistor R_{c1 }is calculated using the approximation:
where D_{MAX} is the maximum duty cycle at the minimum V_{IN} in boost mode and A_{CS} is the current sense amplifier gain. The compensation capacitor C_{c1} is then calculated from:
The standard values of compensation components are selected to be R_{c1} = 10 kΩ and C_{c1} = 22 nF.
A high frequency pole is added to suppress switching noise using a 100 pF capacitor (C_{c2}) in parallel with R_{c1} and C_{c1}. These values provide a good starting point for the compensation design. Each design should be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.